Consumer electronic products such as televisions, digital cameras, cellular telephones, media content players, etc., help to satisfy consumer demand for basic communications and entertainment services. Data storage components play an important role in the operation of these devices. Data storage devices include RAM, ROM, flash memory products, etc.
An important feature of data storage devices is memory cell density. There are many approaches to increasing the memory cell density of memory arrays. One approach involves reducing the channel length between the source and the drain of transistors associated with memory cells in a memory array. This allows the size of each memory cell to be reduced which in turn facilitates the provision of denser memory arrays. Another approach to increasing memory cell density is embodied in a commercially available flash memory product called MirrorBit™ Technology from Spansion, located in Sunnyvale, Calif.
In flash memory arrays that use MirrorBit technology, the use of MirrorBit memory cells effectively doubles their intrinsic density by storing two physically distinct bits on opposite sides of the memory cells. Each bit that is stored within a cell serves as a binary unit of data (either a logic one or zero) that is mapped directly to the memory array.
An exemplary MirrorBit™ memory device includes a semiconductor substrate with spaced apart source and a drain regions (both typically having N-type conductivity) formed in a substrate. An oxide-nitride-oxide (ONO) layered stack is formed on the top surface of the substrate between the source and drain regions. A gate electrode, which typically comprises an N or N+ polysilicon layer, is formed over the ONO stack to provide a silicon-oxide-nitride-oxide (SONOS) structure. The ONO stack includes a first or bottom dielectric layer (often referred to as a bottom tunnel oxide), a charge storing nitride layer, and a second or top dielectric layer of oxide.
Some challenges associated with SONOS devices are related to structural and functional features of the device. For example, it can be difficult to reduce the size or pitch of the cell because the storage element of the above-mentioned flash memory cell can be planar (the oxide, nitride and oxide layers are all horizontal layers formed one on top of the other on the silicon substrate). Moreover, during the erasure of a SONOS memory cell such as by hot hole injection, because hot holes bombard the interface between the substrate and the bottom tunnel oxide, the interface as well as the bottom tunnel oxide can be damaged causing undesirable interface states and degraded reliability over program/erase cycling.
Some conventional SONOS devices use shallow trench isolation (STI) structures that define the device active area. Conventional fabrication methodologies that form such structures can yield results that can affect the operation of the fabricated SONOS devices. Problematic features of devices fabricated from conventional methodologies include localized electron injection at the corners of the active area STI structures when these structures feature uniform bottom oxide coverage. This localized electron injection can degrade reliability. In particular, it should be appreciated that localized electron injection at corners between the top surface of an STI structure and its sidewalls can contribute to early breakdown.
FIG. 1 shows a conventional ONO memory structure 100. Memory structure 100 includes semiconductor structure 101, bottom oxide 103, nitride layer 105 and top oxide 107. It should be appreciated that as devices such as ONO memory structure 100 are made smaller, localized electron injection at corners (see A and B in FIG. 1) of semiconductor structure 101 becomes more severe. As discussed above, such localized electron injection can contribute to breakdown of bottom oxide 103 at these points. It should be appreciated that a breakdown of bottom oxide 103 can cause a loss of charge for the charge storage cell structure. As a result, the reliability of the device suffers as programmed data can be lost.
As can be seen from the above discussion, conventional approaches to fabricating memory cells can provide poor results. These approaches can yield devices with features that negatively affect device function and degrade reliability.